Digital Core Design

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DTPCI32DC

Dual Clock 32bit PCI Bus Target Interface

    The DTPCI32DC is a 32-bit target interface which provides all requirements of the PCI 3.0 specification for a target device. It compromises a minimal gate count with a high-bandwidth data transfer. Core’s main feature is a presence of two clock domains. They enable a flexibility and a higher performance as well. When time required for implementation becomes crucial, the DTPCI32DC brings domain crossing. Saved time can be used for a specific system implementation instead. The user-friendly back-end interface can be very easily and effectively tailored to the design needs.
    The Core supports up to six Base Address Registers and Expansion Rom address register with both I/O and Memory space decoding from 16 bytes up to 4 GB. Another important feature is a cache wrapping hardware support and a cacheline pre-fetching capability. The DTPCI32DC is accepting size cache lines which are powered from 2 up to 128. It enables also target-disconnect with data, without data or by a target abort. Moreover, the DTPCI32DC is capable to work with 66 MHz clock frequency in the most popular technologies. It assures the PCI timing requirements, as well as other parameters like FIFOs depths number or Base Address Registers (they can be easily configured at the pre-synthesis stage).


    Key Features

    ● Fully supports PCI specification 3.0 protocol
    ● Stable clock domain crossing regardless of the clock frequencies
    ● Cache wrapping (cache lines must be powers of 2)
    ● User controlled burst data transfer
    ● Possible no-wait state transactions
    ● Automatic handling of configuration space read/write access
    ● Parity generation and parity error detection
    ● Single interrupt support
    ● Configurable FIFOs depth
    ● Supported backend initiated burst termination (with and without data)
    ● No tri-state buffers

    Applications

    The DTPCI32DC offers a highly customizable and scalable solution, designed to meet the requirements of various applications.


    Symbol

     pci_clk
     pci_rst
     pci_adi
     bend_clk
    bend_rsto 
     bend_datai
    bend_addr 
    bend_datao 
    bend_ben 
    bend_wr 
    bend_rd 
     pci_cbe
     pci_frame
     pci_trdy
    pci_ado 
     pci_irdy
     pci_idsel
    pci_stop 
    pci_devsel 
    pci_paro 
     bend_last
     bend_term
     bend_status
    bend_dir 
    bend_comm 
     pci_pari
    pci_paro 
    pci_perr 
    pci_serr 
    pci_aden 

    Pins description

    PinTypeDescription
    pci_clkinputPCI clock
    pci_rstinputPCI main reset
    pci_adiinputPCI input address / data bus
    bend_clkinputBack-end clock
    bend_dataiinputInput data bus
    pci_cbeinputPCI command/byte enables
    pci_frameinputPCI start of the frame indication
    pci_trdyinputTarget ready
    pci_irdyinputInitiator ready
    pci_idselinputPCI configuration device selection
    bend_lastinputTerminate with data
    bend_terminputTerminate without data
    bend_statusinputBeck-end command register from configuration space
    pci_pariinputPCI input parity
    bend_rstooutputBack-end synchronised reset
    bend_addroutputBack-end address
    bend_dataooutputOutput data bus
    bend_benoutputBack-end bit enables
    bend_wroutputWrite enable
    bend_rdoutputRead enable
    pci_adooutputPCI output address/data bus
    pci_stopoutput 
    pci_devseloutput 
    pci_parooutputPCI output parity
    bend_diroutputTransaction direction
    bend_commoutputBack-end command register from configuration space
    pci_parooutputPCI output parity
    pci_perroutputPCI parity error
    pci_serroutputPCI system error
    pci_adenoutput 

    Block Diagram

    Address DecoderIt is responsible for decoding the addresses which have been previously written into the base address registers in the configuration space. Cacheline wrapping decoding is also realized by this module.
    pci_clk
    pci_rst
    pci_adi
    Back-end ControllerResponsible for the back-end address generation and also cache wrapping and cacheline prefetching.
    bend_clk
    bend_rsto
    Outgoing FIFO ControllerThese modules are responsible for synchronization of data between the domains. The pointers of FIFOs are encoded in the grey code.
    bend_addr
    bend_datai
    bend_datao
    bend_ben
    bend_wr
    bend_rd
    Configuration SpaceIt holds information about status of the DTPCI32DC and also controls its behavior. It contains the base address registers which encodes the addressing spaces and sizes.
    pci_cbe
    pci_ado
    pci_frame
    pci_trdy
    Command DecoderResponsible for decoding to the control flags which are encoded in the PCI_CBE strobe.
    pci_irdy
    pci_stop
    pci_devsel
    pci_idsel
    pci_paro
    Incoming FIFO ControllerThese modules are responsible for synchronization of data between the domains. The pointers of FIFOs are encoded in the grey code.
    bend_dir
    bend_last
    bend_term
    bend_comm
    bend_status
    Parity ModuleGenerating the parity and checking if the parity input matches the calculated value and also parity and system error generation.
    pci_pari
    pci_paro
    pci_perr
    pci_serr
    pci_aden
    PCI synchronizers
    Back-end synchronizers
    DTPCI32DC data Internal connection

    Units

    Address Decoder
    It is responsible for decoding the addresses which have been previously written into the base address registers in the configuration space. Cacheline wrapping decoding is also realized by this module.
    Back-end Controller
    Responsible for the back-end address generation and also cache wrapping and cacheline prefetching.
    Outgoing FIFO Controller
    These modules are responsible for synchronization of data between the domains. The pointers of FIFOs are encoded in the grey code.

    Configuration Space
    It holds information about status of the DTPCI32DC and also controls its behavior. It contains the base address registers which encodes the addressing spaces and sizes.
    Command Decoder
    Responsible for decoding to the control flags which are encoded in the PCI_CBE strobe.
    Incoming FIFO Controller
    These modules are responsible for synchronization of data between the domains. The pointers of FIFOs are encoded in the grey code.

    Parity Module
    Generating the parity and checking if the parity input matches the calculated value and also parity and system error generation.
    PCI synchronizers
    Back-end synchronizers