Digital Core Design

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DSPI

Serial Peripheral Interface – Master/Slave

    The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data are simultaneously transmitted and received. What's the most important, it's a technology independent design that can be implemented in a variety of process technologies.
    The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. It can be configured as a master or a slave device, with data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock.
    The DSPI automatically drive selected by SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. What's more important, error-detection logic is included to support interprocessor communications. A write collision detector indicates, when an attempt is made, to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI devices simultaneously attempts to become bus master.
    What does it mean for you? The DSPI is fully customizable, which means that we deliver it tailored to your configuration and requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.


    Key Features

    • SPI Master
      • Master and Multi-master operations
      • 8 SPI slave select lines
      • System error detection
      • Mode fault error
      • Write collision error
      • Interrupt generation
      • Supports speeds up 1/4 of system clock
      • Bit rates generated 1/4 - 1/512 of system clock.
      • Four transfer formats supported
      • Simple interface allows easy connection to microcontrollers
    • SPI Slave
      • Slave operation
      • System error detection
      • Interrupt generation
      • Supports speeds up 1/4 of system clock
      • Simple interface allows easy connection to microcontrollers
      • Four transfer formats supported
    • Available system interface wrappers:
      • AMBA - APB Bus
      • Altera Avalon Bus
      • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready

    Applications

    • Embedded microprocessor boards
    • Consumer and professional audio/video
    • Home and automotive radio
    • Low-power applications
    • Communication systems
    • Digital multimeters

    Symbol

     mi
     si
    mo 
    so 
     scki
    scko 
     ss
    scken 
    sso (7:0) 
    int 
    soen 
     datai (7:0)
     rd
     wr
     addr (1:0)
     cs
    datao (7:0) 

    Pins description

    PinTypeDescription
    miinputMaster serial data input
    siinputSlave serial data input
    sckiinputSPI clock input
    ssinputSlave select
    datai (7:0)inputData bus input
    rdinputProcessor read strobe
    wrinputProcessor write strobe
    addr (1:0)inputProcessor address lines
    csinputChip select
    mooutputMaster serial data output
    sooutputSlave serial data output
    sckooutputSPI clock output
    sckenoutputSPI clock output enable
    sso (7:0)outputSlave select outputs
    intoutputInterrupt request
    soenoutputSlave output enable
    datao (7:0)outputData bus output

    Block Diagram

    Shift registerShift register is a core element of every SPI system. It is single buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter, until the previous transaction is complete. However, received data is transferred into a parallel read data buffer, so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer, before the next serial character is ready to be transferred, no overrun condition will occur. When an SPI transfer occurs, an 8-bit character is shifted out on data pin, while a different 8-bit character is simultaneously shifted in a second data pin. There is also another way to view this transfer, while 8-bit shift register in the master and another 8-bit shift register in the slave are connected, as a circular 16-bit shift register. When transfer occurs, this distributed shift register is moved 8-bit positions; thus, the characters in the master and slave are effectively exchanged.
    mi
    mo
    si
    so
    SPI Clock LogicSoftware can select any from four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow master device communication with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral.
    scki
    scko
    SPI ControllerThe SPI Controller manages the Master/Slave operation and controls the transmission. It also manages the transmission speed and format (Phase and polarity). Controller itself generates interrupt request and detects transmission errors.
    scken
    ss
    sso (7:0)
    int
    soen
    Control RegistersThe Control Registers module contains all DSPI internal data, control and status registers.

    SPI Data Register (SPDR) is in fact double register - write only transmitter data register and read only receiver data register.

    Control Register may be read or written at any time, is used to configure the DSPI system. This register controls the mode of transmission (Master, Slave), polarity and phase of SPI Clock and transmission speed.

    Status Register (SPSR) contains flags, indicating the completion of transfer or occurrence of system errors. All flags are set automatically when the corresponding event occur and cleared by software sequence.

    Slave Select Control Register configures which slave select output should be driven while SPI master transfer. Contents of SSCR register is automatically assigned on SS7O-SS0O pins when DSPI master transmission starts.

    FIFO Control Register (FCR) available only in DSPI_FIFO mudule equipped with the FIFOs transmitter and receiver. FCR contains control bit, which configure receiver trigger level, enables FIFO mode, defines FIFO size and enables DMA mode.
    datai (7:0)
    datao (7:0)
    rd
    wr
    addr (1:0)
    cs
    SPI bus SPI virtual bus

    Units

    Shift register
    Shift register is a core element of every SPI system. It is single buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter, until the previous transaction is complete. However, received data is transferred into a parallel read data buffer, so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer, before the next serial character is ready to be transferred, no overrun condition will occur. When an SPI transfer occurs, an 8-bit character is shifted out on data pin, while a different 8-bit character is simultaneously shifted in a second data pin. There is also another way to view this transfer, while 8-bit shift register in the master and another 8-bit shift register in the slave are connected, as a circular 16-bit shift register. When transfer occurs, this distributed shift register is moved 8-bit positions; thus, the characters in the master and slave are effectively exchanged.
    SPI Clock Logic
    Software can select any from four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow master device communication with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral.
    SPI Controller
    The SPI Controller manages the Master/Slave operation and controls the transmission. It also manages the transmission speed and format (Phase and polarity). Controller itself generates interrupt request and detects transmission errors.

    Control Registers
    The Control Registers module contains all DSPI internal data, control and status registers.

    SPI Data Register (SPDR) is in fact double register - write only transmitter data register and read only receiver data register.

    Control Register may be read or written at any time, is used to configure the DSPI system. This register controls the mode of transmission (Master, Slave), polarity and phase of SPI Clock and transmission speed.

    Status Register (SPSR) contains flags, indicating the completion of transfer or occurrence of system errors. All flags are set automatically when the corresponding event occur and cleared by software sequence.

    Slave Select Control Register configures which slave select output should be driven while SPI master transfer. Contents of SSCR register is automatically assigned on SS7O-SS0O pins when DSPI master transmission starts.

    FIFO Control Register (FCR) available only in DSPI_FIFO mudule equipped with the FIFOs transmitter and receiver. FCR contains control bit, which configure receiver trigger level, enables FIFO mode, defines FIFO size and enables DMA mode.