Digital Core Design

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D16450

Configurable UART

    The D16450 is a soft core of the Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C450. It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The CPU can read a complete status of the UART at any time, during the functional operation. Reported information status  includes the type and a condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16450 includes a programmable baud rate generator, which is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. Our proprietary solution has also a complete MODEM control capability and a processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing the computing required to handle the communication link.
    The separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.
    The core is perfect for applications, where the UART core and a microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. Our solution is also dedicated for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to the D16450 universal interface, both, core implementation and verification, are very simple. They could be done by only eliminating a number of clock trees in the complete system.

    The D16450 includes a fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. 
    Our trustworthy solution is a technology independent design, that can be implemented in a variety of process technologies.


    Family summary

    UART Feature DμART D2692 D16450 D16550 D16750 D16552 D16752 D16950 D85C30
    FIFO Size - 2*8 - 2*16 2*64 4*16 x*2*64 2*128 4
    Multichannel option - - - - - + + - -
    Separate BAUD Clock line + - + + + + + + +
    Modem Control - - + + + + + + +
    False Start Bit detection + + + + + + + + +
    Status report + + + + + + + + +
    Internal diagnostic capabilities + + + + + + + + +
    Prioritized interrupt system - + + + + + + + +
    Break generation and detection - + + + + + + + +
    Fast mode CLK/4 - - - - o - o + -
    Half-Duplex RS485 - + - - o - o + +
    RS485 buffer enable - - - + + - + + +
    IRDA support - - - - o + - + -
    Additional CLK prescaler - - - - - - + - -
    1284 Parallel Port - - - - - + - - -
    Hardware flow control RTS/CTS - + - - + - + + +
    Software flow control Xon/Xoff - - - - - - + + -
    Isochronous mode - - - - - - - + +
    Detector of bad data in receiver FIFO - + - + + + + + +
    Special character detection - - - - - - + + -
    Software channel reset - - - - - - - + -
    4 byte device ID - - - - - - - + -
    Trigger levels for receiver and transmitter - - - - - - - + -
    Hardware flow control DTS/DTR - - - - - - - + -
    Optional FIFO size extension to 512 bytes - - - - + - + - -

    The main features of each UART family member have been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application.

    Key Features

    • Software compatible with 16450 UART
    • Configuration capability
    • Separate configurable BAUD clock line
    • Majority Voting Logic
    • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
    • Independently controlled transmit, receive, line status and data set interrupts
    • False start bit detection
    • 16 bit programmable baud generator
    • Independent receiver clock input
    • MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
    • Fully programmable serial-interface characteristics:
      • 5-, 6-, 7-, or 8-bit characters
      • Even, odd, or no-parity bit generation and detection
      • 1-, 1,5-, or 2-stop bit generation
      • Internal baud generator
    • Complete status reporting capabilities
    • Line break generation and detection. Internal diagnostic capabilities:
      • Loop-back controls for communications link fault isolation
      • Break, parity, overrun, framing error simulation
    • Full prioritized interrupt system controls
    • Available system interface wrappers:
      • AMBA - APB Bus
      • Altera Avalon Bus
      • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design and no internal tri-states

    Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

    Configuration

    The following parameters of the D16450 core can be easy adjusted to requirements of dedicated application and technology. Core configuration can be prepared by effortless changing appropriate constants in package file. There is no need to change any part of the code.

    • Baud generator: enable / disable
    • External RCLK source: enable / disable
    • External BAUDCLK source: enable / disable
    • Asynchronous input buffer: enable / disable
    • Modem Control: enable / disable
    • SCR register: enable / disable

    Symbol

     clk
     rst
    so 
    temt 
     rclk
     si
    intr 
     baudclken
     baudclk
    baudout 
    so 
     datai (7:0)
     rd
     wr
     cs
     addr (2:0)
    datao (7:0) 

    Pins description

    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    rclkinputReceiver clock
    siinputSerial data input
    baudclkeninputBaud generator clock enable
    baudclkinputBaud generator clock
    datai (7:0)inputParallel data input
    rdinputRead input
    wrinputWrite signal input
    csinputChip select input
    addr (2:0)inputAddress bus input
    sooutputSerial data output
    temtoutputTransmitter Empty - used to control RS485 buffer
    introutputInterrupt request output
    baudoutoutputBaud generator output
    sooutputSerial data output
    datao (7:0)outputParallel data bus output

    Block Diagram

    Transmitter ControlTransmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    so
    temt
    Receiver ControlThe D16X50 receiver has its own independent clock input RCLK. Receiving starts when the falling edge on Serial Input (SI) during IDLE State is being detected. After starting, the SI input is sampled every 16 RCLK cycles, as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.
    rclk
    si
    Interrupt ControllerD16X50 UARTs got fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers.
    intr
    Baud GeneratorThe UART contains a programmable 16 bit baud generator, that divides clock input by a divisor, in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate. The formula for the divisor is:

    divisor=frequency/(16*baudrate)

    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM, to prevent long counts on initial load.
    baudout
    baudclken
    baudclk
    Transmitter controllerTransmitter Control module controls transmission of written to THR (Transmitter Holding register) character via serial output SO. The new transmission starts on the next overflow signal of internal baud generator (the worst case delay is: 1 baudout cycle) after writing to THR. Transmission control contains THR register and transmitter shift register.
    so
    Data Bus BufferData Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low. Both RD and WR are qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.
    datai (7:0)
    rd
    wr
    cs
    addr (2:0)
    datao (7:0)
    clk
    rst
    D16550 D16XXX UART internal data bus

    Units

    Transmitter Control
    Transmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    Receiver Control
    The D16X50 receiver has its own independent clock input RCLK. Receiving starts when the falling edge on Serial Input (SI) during IDLE State is being detected. After starting, the SI input is sampled every 16 RCLK cycles, as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.
    Interrupt Controller
    D16X50 UARTs got fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers.

    Baud Generator
    The UART contains a programmable 16 bit baud generator, that divides clock input by a divisor, in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate. The formula for the divisor is:

    divisor=frequency/(16*baudrate)

    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM, to prevent long counts on initial load.
    Transmitter controller
    Transmitter Control module controls transmission of written to THR (Transmitter Holding register) character via serial output SO. The new transmission starts on the next overflow signal of internal baud generator (the worst case delay is: 1 baudout cycle) after writing to THR. Transmission control contains THR register and transmitter shift register.
    Data Bus Buffer
    Data Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low. Both RD and WR are qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.