Digital Core Design

The Power of Intellectual Property

D16752

Configurable UART with FIFO, hardware and software flow control

    The D16752 is a universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs and automatic hardware/software flow control. It offers enhanced features, like transmission control register (TCR), that stores received FIFO threshold level, to start/stop transmission during hardware and sofware flow control. With the FIFO RDY register, the software gets a status of TXRDY/RXRDY for all UART ports in one access. Onboard status registers provide the user with error indications and an operational status modem interface control. System interrupts may be tailored to meet your requirements. An internal loopback capability allows onboard diagnostics. The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7 or 8 bits. The UART has a 64-byte receive FIFO and a transmit FIFO, which can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate, based upon a programmable divisor and its input clock. It can transmit even, odd or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle or framing errors, FIFO overflow and parity errors. On the other hand, the transmitter can detect a FIFO underflow. The UART also contains a software interface for modem control operations and has a software flow control, combined with hardware flow control capabilities. The D16752 is software compatible with the TL16C752 . It provides few enhanced features, which are provided through a special enhanced feature register. The UART will perform a serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the D16752 can be read by the CPU at any time during functional operation. Our efficient core can be placed in an alternate mode (FIFO mode), relieving the processor of excessive software overhead, which is run by buffering received/transmitted characters. Both, the receiver and the transmitter FIFOs, can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers. The D16752 has a selectable hardware flow control and a software flow control.
    The hardware flow control significantly reduces software overhead and increases system efficiency, by automatically controlled serial data flow using the RTS output and CTS input signals.
    Software flow control automatically monitors data flow, by using programmable Xon/Xoff characters.The UART includes a programmable baud rate generator, that can divide the timing reference clock input by a divisor between 1 and (216–1).

    The separate BAUD CLK line allow to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.

    D16752 includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. Our efficient Core is a technology independent design, that can be implemented in a variety of process technologies.

    The configuration capability allows you to enable or disable during the Synthesis process the Modem Control Logic and the FIFO's Control Logic and change the FIFO size. So, in applications with area limitation and where the UART works only in a 16450 mode, disabling the Modem Control and FIFO's allow to save about 50% of logic resources.

    The Core is perfect for applications, where the UART core and a microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. Nevertheless, our solution is designed for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks the D16752, the CPU interface core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.

    The D16752 UART Core can operate as dual channel, as well as single channel UART.


    Family summary

    UART Feature DμART D2692 D16450 D16550 D16750 D16552 D16752 D16950 D85C30
    FIFO Size - 2*8 - 2*16 2*64 4*16 x*2*64 2*128 4
    Multichannel option - - - - - + + - -
    Separate BAUD Clock line + - + + + + + + +
    Modem Control - - + + + + + + +
    False Start Bit detection + + + + + + + + +
    Status report + + + + + + + + +
    Internal diagnostic capabilities + + + + + + + + +
    Prioritized interrupt system - + + + + + + + +
    Break generation and detection - + + + + + + + +
    Fast mode CLK/4 - - - - o - o + -
    Half-Duplex RS485 - + - - o - o + +
    RS485 buffer enable - - - + + - + + +
    IRDA support - - - - o + - + -
    Additional CLK prescaler - - - - - - + - -
    1284 Parallel Port - - - - - + - - -
    Hardware flow control RTS/CTS - + - - + - + + +
    Software flow control Xon/Xoff - - - - - - + + -
    Isochronous mode - - - - - - - + +
    Detector of bad data in receiver FIFO - + - + + + + + +
    Special character detection - - - - - - + + -
    Software channel reset - - - - - - - + -
    4 byte device ID - - - - - - - + -
    Trigger levels for receiver and transmitter - - - - - - - + -
    Hardware flow control DTS/DTR - - - - - - - + -
    Optional FIFO size extension to 512 bytes - - - - + - + - -

    The main features of each UART family member have been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application.

    Key Features

    • Software compatible with 16752 UARTs
    • Configuration capability
    • Dual channel UART - configurable
    • Separate configurable BAUD clock line
    • Supports RS232 and RS485 standards
    • Hardware/Software Data flow control
      • Programmable Xon/Xoff characters
      • Programmable AutoRTS, AutoCTS
    • Programmable and selectable Transmit and Receive FIFO Trigger levels for DMA and interrupt generation
    • Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control
    • Software Flow Control Turned OFF, optionally by any Xon Rx Character
    • Software Selectable Baud Rate Generator Prescaleable Clock Rates of 1x and 4x
    • Programmable SLEEP Mode
    • Majority Voting Logic
    • Two modes of operation: UART mode and FIFO mode
      • In the FIFO mode transmitter and receiver are each buffered with 64 byte FIFO to reduce the number of interrupts presented to the CPU
      • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
    • Configurable FIFO size allowing up to 512 levels deep FIFOs in both Rx and Tx directions.
    • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
    • Independently controlled transmit, receive, line status and data set interrupts
    • False start bit detection
    • 16 bit programmable baud generator
    • MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
    • Fully programmable serial interface characteristics:
      • 5-, 6-, 7- or 8-bit characters
      • Even, odd, or no-parity bit generation and detection
      • 1-, 1.5-, or 2-stop bit generation
      • Internal baud generator
    • Complete status reporting capabilities
    • Line break generation and detection. Internal diagnostic capabilities:
      • Loop-back controls for communications link fault isolation
      • Break, parity, overrun, framing error simulation
    • Full prioritized interrupt system controls
    • Available system interface wrappers:
      • AMBA - APB Bus
      • Altera Avalon Bus
      • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design and no internal tri-states

    Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

    Configuration

    The following parameters of the D16752 core can be easily adjusted to requirements of dedicated application and technology. Core configuration can be effortlessly done by changing appropriate constants in package file. There is no need to change any parts of the code.

    • Baud generator: enable / disable
    • External BAUDCLK source: enable / disable
    • Channel B: enable / disable
    • Modem Control: enable / disable
    • SCR register: enable / disable
    • FIFO Control logic: enable / disable
    • FIFO Size: normal 64 / large, up to 512

    Symbol

     clk
     rst
     rx a / b
    tx a / b 
     baudclk a / b
     bauden a / b
     datai (7:0)
     addr (2:0)
     wr
     rd
     cs a / b
    datao (7:0) 
     cts a / b
     dsr a / b
     dsr a / b
     ri a / b
    rts a / b 
    dtr a / b 
    op a / b 
    intr a / b 

    Pins description

    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    rx a / binputSerial Data input
    baudclk a / binputBaud Clock input
    bauden a / binputBaud CLK enable
    datai (7:0)inputData Bus input
    addr (2:0)inputAddress Bus
    wrinputWrite Strobe
    rdinputRead enable
    cs a / binputChip Select UART A/B
    cts a / binputClear to send input
    dsr a / binputData set ready input
    dsr a / binputData carrier detect input
    ri a / binputRing indicator input
    tx a / boutputSerial Data output
    datao (7:0)outputData Bus Output
    rts a / boutputRequest to send output
    dtr a / boutputData terminal ready output
    op a / boutputUser Defined Output
    intr a / boutputInterrupt request

    Block Diagram

    Receiver BufferThe Rx FIFO can be 64 (128, 256, 512) levels deep, it receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time, if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it is full, and will not accept any next byte. Any more data entering the Rx shift register will set the Overrun Error flag.
    Receiver Control UnitReceiving starts, when the falling edge on Serial Input (RX) during IDLE State is detected. After starting the SI input is sampled every 16 RCLK cycles as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.
    rx a / b
    Transmitter BufferThe Tx portion of the UART transmits data through TX, as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO, if it currently holds 64 (128, 256, 512) characters (depending on FCR [5] bit value and selected FIFO size). Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt.
    Transmitter Control UnitTransmitter Control module controls transmission of written to THR (Transmitter Holding register) character via serial output TX. The new transmission starts on the next overflow signal of internal baud generator, after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    tx a / b
    Baud Rate GeneratorThe UART contains a programmable 16 bit baud generator, that divides clock input by a divisor in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate.
    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge, following the write to DLL or DLM to prevent long counts on initial load.
    baudclk a / b
    bauden a / b
    Data Bus BufferThe data Bus Buffer accepts inputs from the system bus and generates control signals for the other D1675X functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WE signals are active low, and are qualified by CS A / B / C / D; RD and WE are ignored unless the D1675X has been selected by holding CS low.
    datai (7:0)
    datao (7:0)
    addr (2:0)
    wr
    rd
    cs a / b
    Modem ControllerModem Controller monitors the interface with the MODEM, data set or a peripheral device emulating a MODEM.
    rts a / b
    cts a / b
    dsr a / b
    dsr a / b
    ri a / b
    dtr a / b
    op a / b
    Interrupt ControllerInterrupt Controller contains fully prioritized interrupt system controller. It monitors interrupt requests to the CPU and interrupt priority. IC ia also equipped with Interrupt Enable (IER) and Interrupt Identification (IIR) registers.
    intr a / b
    clk
    rst
    D16550 D16XXX UART internal data bus

    Units

    Receiver Buffer
    The Rx FIFO can be 64 (128, 256, 512) levels deep, it receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time, if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it is full, and will not accept any next byte. Any more data entering the Rx shift register will set the Overrun Error flag.
    Receiver Control Unit
    Receiving starts, when the falling edge on Serial Input (RX) during IDLE State is detected. After starting the SI input is sampled every 16 RCLK cycles as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.
    Transmitter Buffer
    The Tx portion of the UART transmits data through TX, as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO, if it currently holds 64 (128, 256, 512) characters (depending on FCR [5] bit value and selected FIFO size). Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt.

    Transmitter Control Unit
    Transmitter Control module controls transmission of written to THR (Transmitter Holding register) character via serial output TX. The new transmission starts on the next overflow signal of internal baud generator, after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    Baud Rate Generator
    The UART contains a programmable 16 bit baud generator, that divides clock input by a divisor in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate.
    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge, following the write to DLL or DLM to prevent long counts on initial load.
    Data Bus Buffer
    The data Bus Buffer accepts inputs from the system bus and generates control signals for the other D1675X functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WE signals are active low, and are qualified by CS A / B / C / D; RD and WE are ignored unless the D1675X has been selected by holding CS low.

    Modem Controller
    Modem Controller monitors the interface with the MODEM, data set or a peripheral device emulating a MODEM.
    Interrupt Controller
    Interrupt Controller contains fully prioritized interrupt system controller. It monitors interrupt requests to the CPU and interrupt priority. IC ia also equipped with Interrupt Enable (IER) and Interrupt Identification (IIR) registers.