Digital Core Design

The Power of Intellectual Property

D8254

Programmable Interval Timer

    The D8254 is a programmable interval timer/counter, binary compatible with the 82C54 industry standard. Since DCD's core value is innovation, this unique IP Core solves one of the most common problems in any micro-computer system: the generation of accurate time delays under software control. The D8254 can be used as:

       • Real time clock
       • Even counter
       • Digital one-shot
       • Programmable rate generator
       • Square wave generator
       • Binary rate multiplier
       • Complex waveform generator
       • Complex motor controller
       • Interrupt on terminal count
     

    The D8254 includes fully automated testbench with complete set of tests , which allows an easy package validation at each stage of SoC design flow.Our proprietary core is a technology independent design, that can be implemented in a variety of process technologies.


    Key Features

    • Three independent 16-bit counters
    • Six programmable Counter modes
      • Interrupt on terminal count
      • Hardware retriggerable One-Shot
      • Rate Generator
      • Square wave mode
      • Software triggered strobe
      • Hardware triggered strobe
    • Binary or BCD counting
    • Status Read Back Command
    • Simple interface allows easy connection to microcontrollers
    • Fully synthesizable
    • Static design and no internal tri-states

    Applications

    • Embedded microprocessor boards

    Symbol

     datai (7:0)
    datao (7:0) 
     rst
     cs
     addr (1:0)
     rd
     wr
     clk0
     gate0
    out0 
     clk1
     gate1
    out1 
     clk2
     gate2
    out2 

    Pins description

    PinTypeDescription
    datai (7:0)inputProcessor data bus (input)
    rstinputGlobal reset
    csinputChip select
    addr (1:0)inputProcessor address lines
    rdinputProcessor read strobe
    wrinputProcessor write strobe
    clk0inputClock input for Counter 0
    gate0inputGate input for Counter 0
    clk1inputClock input for Counter 1
    gate1inputGate input for Counter 1
    clk2inputClock input for Counter 2
    gate2inputGate input for Counter 2
    datao (7:0)outputProcessor data bus (output)
    out0outputOutput of Counter 0
    out1outputOutput of Counter 1
    out2outputOutput of Counter 2

    Block Diagram

    Control WordThe Control Word Register is a selected by the Read/Write Logic when ADDR(1:0) = 11. If then the CPU does a write operation to the D8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters.
    Data Bus BufferThe 8-bit buffer is used to interface the D8254 to the system bus.
    datai (7:0)
    datao (7:0)
    Read Write LogicThe Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the D8254. ADDR(1:0) select one of the three counters or the Control Word Register to be read from/written into. A low on the RD input tells the D8254, that the CPU is reading one of the counters. A low on the WR input tells the IP Core, that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the 82C54 has been selected by holding CS low. The WR and CLK signals should be synchronous. This is accomplished by using a CLK input signal to the D8254 counters, which is a derivative of the system clock source. There os also another possibility by synchronizing externally the WR and CLK input signals. This is done by gating WR with CLK.
    rst
    cs
    addr (1:0)
    rd
    wr
    Counter 0All three Counters (0, 1, 2) are functionally identical but fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:
    • Interrupt on terminal count
    • Hardware retriggerable One-Shot
    • Rate Generator
    • Square wave mode
    • Software triggered strobe
    • Hardware triggered strobe
    clk0
    gate0
    out0
    Counter 1All three Counters (0, 1, 2) are functionally identical but fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:
    • Interrupt on terminal count
    • Hardware retriggerable One-Shot
    • Rate Generator
    • Square wave mode
    • Software triggered strobe
    • Hardware triggered strobe
    clk1
    gate1
    out1
    Counter 2All three Counters (0, 1, 2) are functionally identical but fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:
    • Interrupt on terminal count
    • Hardware retriggerable One-Shot
    • Rate Generator
    • Square wave mode
    • Software triggered strobe
    • Hardware triggered strobe
    clk2
    gate2
    out2
    Data bus Virtual internal data bus

    Units

    Control Word
    The Control Word Register is a selected by the Read/Write Logic when ADDR(1:0) = 11. If then the CPU does a write operation to the D8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters.
    Data Bus Buffer
    The 8-bit buffer is used to interface the D8254 to the system bus.
    Read Write Logic
    The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the D8254. ADDR(1:0) select one of the three counters or the Control Word Register to be read from/written into. A low on the RD input tells the D8254, that the CPU is reading one of the counters. A low on the WR input tells the IP Core, that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the 82C54 has been selected by holding CS low. The WR and CLK signals should be synchronous. This is accomplished by using a CLK input signal to the D8254 counters, which is a derivative of the system clock source. There os also another possibility by synchronizing externally the WR and CLK input signals. This is done by gating WR with CLK.

    Counter 0
    All three Counters (0, 1, 2) are functionally identical but fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:
    • Interrupt on terminal count
    • Hardware retriggerable One-Shot
    • Rate Generator
    • Square wave mode
    • Software triggered strobe
    • Hardware triggered strobe
    Counter 1
    All three Counters (0, 1, 2) are functionally identical but fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:
    • Interrupt on terminal count
    • Hardware retriggerable One-Shot
    • Rate Generator
    • Square wave mode
    • Software triggered strobe
    • Hardware triggered strobe
    Counter 2
    All three Counters (0, 1, 2) are functionally identical but fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:
    • Interrupt on terminal count
    • Hardware retriggerable One-Shot
    • Rate Generator
    • Square wave mode
    • Software triggered strobe
    • Hardware triggered strobe