Digital Core Design

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D6840

Programmable Timer Module

    The D6840 is a programmable timer module, compatible with the 6840 industry standard. It was designed to be used in a peripheral device for D68xx processors. Moreover, our proprietary IP Core works perfectly as a separate module in applications, where 6840 timer features are useful. The D6840 has three separate 16-bit timers, with individual control and common status registers. The timers may be used for square wave generation with duty cycle regulation. The signal may then be generated as a continuous wave or a single-shot mode. But this is not all - our unique module can be used for frequency or pulse width measurement and comparison. The D6840 has an interrupt, which is useful in a controlling module by the CPU.
    As all of our solutions, the D6840 is a technology independent design, that can be implemented in a variety of process technologies.


    Key Features

    • Compatible with 6840 industry standard
    • Three separate timers
    • Two operation modes
      • Wave synthesis
      • Wave measurement
    • Two generation modes
      • Continuous
      • Single shot
    • Gating system for each clock input
    • Separate timer outputs
    • Prescaler mode for timer3 input clock
    • External clock or E clock used for timer decrement
    • Interrupt generation
    • Split bus for input and output data
    • Fully synthesizable
    • Static synchronous design and no internal tri-states

    Applications

    • External module for D68xx processors
    • Gated wave generation
    • Pulse width modulation
    • Frequency measurement and comparison
    • Pulse width measurement and comparison

    Symbol

     e
     reset
     clk
     g3
    o3 
     c3
     datai (7:0)
     rs (2:0)
     rw
     cs0
     cs1
    irq 
    datao (7:0) 
     c1
     g1
    o1 
     c2
     g2
    o2 

    Pins description

    PinTypeDescription
    einputE clock input
    resetinputGlobal reset
    clkinputGlobal clock
    g3inputTimer 3 clock gate input
    c3inputTimer 3 external clock input
    datai (7:0)inputData bus input
    rs (2:0)inputRegister select
    rwinputRead/write control
    cs0inputChip select 0
    cs1inputChip select 1
    c1inputTimer 1 external clock input
    g1inputTimer 1 clock gate input
    c2inputTimer 2 external clock input
    g2inputTimer 2 clock gate input
    o3outputTimer 3 output
    irqoutputInterrupt request
    datao (7:0)outputData bus output
    o1outputTimer 1 output
    o2outputTimer 2 output

    Block Diagram

    Timer 3Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    g3
    o3
    C3 prescallerClock divider for C3 input. Used for divide clock by 8, in prescaled mode of timer3.
    c3
    CPU interfacePerforms access to internal registers from CPU. This module contains all control and status registers. There is also MSB and LSB buffer used for access to 16-bit counter and Latch.
    irq
    datai (7:0)
    datao (7:0)
    rs (2:0)
    rw
    cs0
    cs1
    Timer 1Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    c1
    g1
    o1
    Timer 2Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    c2
    g2
    o2
    e
    reset
    clk
    D6840 bus Internal connections bus

    Units

    Timer 3
    Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    C3 prescaller
    Clock divider for C3 input. Used for divide clock by 8, in prescaled mode of timer3.
    CPU interface
    Performs access to internal registers from CPU. This module contains all control and status registers. There is also MSB and LSB buffer used for access to 16-bit counter and Latch.

    Timer 1
    Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.
    Timer 2
    Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt.