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DFPAU-DP

Floating Point Arithmetic Coprocessor - Double Precision

    The DFPAU-DP is a Floating Point Arithmetic Coprocessor, designed to assist the CPU in performing floating point arithmetic computations. Our reliable solution replaces directly C software functions by equivalent, very fast hardware operations, which significantly accelerate the system performance. It does not require any programming, as well as no modifications to be made in the main software. Everything is executed automatically during software compilation, by the DFPAU-DP C driver. Our efficient coprocessor was designed to operate with DCD’s DP8051, but can also operate with any other 8-, 16- and 32-bit processor. Drivers for all popular 8051 C compilers are delivered together with the DFPAU-DP package.
    It uses specialized algorithms to compute math functions, like:  addition, subtraction, multiplication, division, square root and comparison. The DFPAU-DP has built-in conversion instructions, from integer type to floating point type and vice versa. The input numbers' format has been developed according to the IEEE-754 standard. Our Floating Point Arithmetic Coprocessor supports double and single precision real numbers: 8-bit, 16-bit and 32-bit integers. This proprietary solution is ready to be used with 8-, 16- and 32-bit processors.

    The DFPAU-DP is a technology independent design, which can be implemented in various process technologies.


    Family summary

    Design Standard compliance Arithmetic operations
    ADD, SUB, MUL, DIV, SQRT, COMP
    Trigonometric operations
    SIN, COS, TAN, ARCTAN
    Processors interfaces
    8,16,32 bit
    Single precision Double precision 8/16/32 bit integers 52-bit integers
    DFPAU IEEE-754 + - + + - - -
    DFPMU IEEE-754 + + + + - + -
    DFPAU-DP IEEE-754 + - + + + + +
    DFPMU-DP IEEE-754 + + + + + + +

    The main features of each Arithmetic Coprocessors family member has been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application.

    Key Features

    • Direct replacement for C double, float software functions such as: +, -, *, /,==, !=,>=, <=, <, >
    • Configurability of all available functions
    • C interface supplied for all popular compilers: GNU C/C++, 8051 compilers
    • No programming required
    • IEEE-754 Double precision real format support – double type
    • IEEE-754 Single precision real format support – float type
    • 8-bit, 16-bit 32-bit and 52-bit integers format supported – integer types
    • Flexible arguments and result registers location
    • Performs the following functions:
      • FADD, FSUB – addition, subtraction
      • FMUL, FDIV – multiplication, division
      • FSQRT – square root
      • FXAM – examine input data
      • FUCOM – comparison
      • FCLD, FILD – 8-bit, 16-bit integer to dou-ble
      • FLLD, FELD – 32-bit, 52-bit integer to double
      • FCST, FIST – double to 8-bit, 16-bi integer
      • FLST, FEST – double to 32-bit, 52-bit integer
      • FFLD – float to double
      • FFST – double to float
    • Exceptions built-in routines
    • Masks each exception indicator:
      • Precision lack PE
      • Underflow result UE
      • Overflow result OE
      • Invalid operand IE
      • Division by zero ZE
      • Denormal operand DE
    • Fully configurable
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready

    Applications

    • Math coprocessors
    • DSP algorithms
    • Embedded arithmetic coprocessor
    • Fast data processing & control

    Symbol

     clk
     rst
     datai1 (31:0)
     addr2 (4:0)
     we
     cs
    datao1 (31:0) 
    irq 

    Pins description

    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    datai1 (31:0)inputData bus input
    addr2 (4:0)inputRegister addres to read/write
    weinputData write enable
    csinputChip select for read/write
    datao1 (31:0)outputData bus output
    irqoutputInterrupt request indicator

    Block Diagram

    AlignIt performs the numbers analyze against IEEE-754 standard compliance. Information about the data classes is passed as a result to appropriate internal module.
    InterfaceMakes interface between external device and core internal 32-bit modules. It contains data, control and status registers. It can be configured to work with 8-, 16- and 32-bit processors..

    1 - data bus can be configured as 8-, 16- or 32- bit depends on processor"s bus size
    2 - address bus is aligned to work with 8- (3:0), 16- (3:1) or 32- (4:2) bit processors
    datai1 (31:0)
    datao1 (31:0)
    irq
    addr2 (4:0)
    we
    cs
    ExponentIt performs operations on exponent part of number. The addition, subtraction, shifting, comparison and conversion operations are executed in this module. It contains exponents and work registers.
    MantissaIt performs operations on mantissa part of number. The addition, subtraction, multiplication, division, square root, comparison and conversion operations are executed in this module. It contains mantissas and work registers.
    ShifterIt performs mantissa shifting during normalization, denormalization operations. Information about out-shifted bits is stored for rounding process.
    Control UnitIt manages execution of all instructions and internal operation required to carry particular function.
    clk
    rst
    Exponent bus Exponent data bus is 17-bit wide bus used for exponent transferring between modules.
    Mantissa Mantissa data bus. It is 70-bit wide internal bus used for mantissas transferring between modules.
    Control bus Control bus is intended for control signals connected to each module. Main control is performed by Control Unit.

    Units

    Align
    It performs the numbers analyze against IEEE-754 standard compliance. Information about the data classes is passed as a result to appropriate internal module.
    Interface
    Makes interface between external device and core internal 32-bit modules. It contains data, control and status registers. It can be configured to work with 8-, 16- and 32-bit processors..

    1 - data bus can be configured as 8-, 16- or 32- bit depends on processor"s bus size
    2 - address bus is aligned to work with 8- (3:0), 16- (3:1) or 32- (4:2) bit processors
    Exponent
    It performs operations on exponent part of number. The addition, subtraction, shifting, comparison and conversion operations are executed in this module. It contains exponents and work registers.

    Mantissa
    It performs operations on mantissa part of number. The addition, subtraction, multiplication, division, square root, comparison and conversion operations are executed in this module. It contains mantissas and work registers.
    Shifter
    It performs mantissa shifting during normalization, denormalization operations. Information about out-shifted bits is stored for rounding process.
    Control Unit
    It manages execution of all instructions and internal operation required to carry particular function.