Digital Core Design

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DP8051XP

Pipelined High Performance Configurable Microcontroller

The DP8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit.
The DP8051XP soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051XP: Harvard, where internal data and program buses are separated and von Neumann, with common program and external data bus. The DP8051XP has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster, than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times more slower than the original implementation, without performance depletion.
The DP8051XP is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's 8051 Core has built-in support for the DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD on Chip Debugger


Family summary

 

Design Dhry
speed
on-chip
CODE
RAM/ROM
off-chip
CODE
CODE
write
IDATA
space
XDATA
space
XDATA,
CODE
wait states
DoCDTM PMU Interrupt
sources
DPTR Timers UART IO Ports Compare/
Capture
Watchdog MDU
MDU32
DI2CM DI2CS DSPI DFPMU DMAC DCAN
DQ80251 75.08 8M 8M + 1k-32k 8M + + +  15 1 3 2 4 + + + + + + + + +
DQ8051CPU 28.40 64k/64k 64k/8M + 256 16M + + +  2 2 - - - - - - - - - - - -
DQ8051 29.01 64k/64k 64k/8M + 256 16M + + +  5 2 2 1 4 - - - - - - - - -
DQ8051XP 29.01 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP8051CPU 15.36 64k/64k 64k/8M + 256 16M + + +  2 1 - - - - - - - - - - - -
DP8051 15.36 64k/64k 64k/8M + 256 16M + + +  5 1 2 1 4 - - - - - - - - -
DP8051XP 15.55 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP80C51 11.46 64k/64k 64k + 256 64k + + +  5 1 2 1 4 - - - - - - - - -
DT8051 8.11 64k/64k 64k + 256 64k - + + 11 1 2 1 1 - - - - - - - - -

The main features of each DCD's DQ8051, DQ80251, DP8051, DP80C51, DT8051 family member have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

CPU Features


Symbol

 reset
 clk
 iprgramsize (2:0)
 iprgromsize (2:0)
 t0
 t1
 gate0
 gate1
 rxd0i
rxd0o 
txd0 
 capture0
 capture1
 capture2
 capture3
 t2
 t2ex
 scli
 sdai
sclo 
sclhs 
sdao 
 tdi
 tck
 tms
tdo 
rtck 
 port0i (7:0)
 port1i (7:0)
 port2i (7:0)
 port3i (7:0)
port0o (7:0) 
port1o (7:0) 
port2o (7:0) 
port3o (7:0) 
 ramdatai (7:0)
ramdatao (7:0) 
ramaddr (7:0) 
ramoe 
ramwe 
 int0
 int1
 int2
 int3
 int4
 int5
 int6
 xdatai (7:0)
 ready
xdatao (7:0) 
xdataz 
xaddr (23:0) 
xprgrd 
xprgwr 
xdatard 
xdatawr 
 sfrdatai (7:0)
sfrdatao (7:0) 
sfrwe 
sfroe 
sfraddr (6:0) 
 rxd1i
rxd1o 
txd1 
 prgramdata (7:0)
 prgromdata (7:0)
prgaddr (15:0) 
prgdatao (7:0) 
prgramwr 
stop 
pmm 
 mosi
 miso
 ss
 sck
sso (7:0) 
 rxclk
 rxdv
 rxer
 rxdata (3:0)
 qmr (7:0)
 txclk
 crs
 col
 qmt (7:0)
 mdi
dmr (7:0) 
waddrmr (10:0) 
raddrmr (10:0) 
enrmr 
enwmr 
txdata (3:0) 
txen 
txer 
dmt (7:0) 
waddrmt (10:0) 
raddrmt (10:0) 
enrmt 
enwmt 
mdo 
mdc 
mdoe 
 sxdmdatai (7:0)
sxdmaddr (15:0) 
sxdmdatao (7:0) 
sxdmoe 
sxdmwe 

Pins description

PinTypeDescription
resetinputGlobal reset
clkinputGlobal clock
iprgramsize (2:0)inputSize of on-chip RAM CODE
iprgromsize (2:0)inputSize of on-chip ROM CODE
t0inputTimer 0 input
t1inputTimer 1 input
gate0inputTimer 0 gate input
gate1inputTimer 1 gate input
rxd0iinputSerial receiver input 0
capture0inputTimer 2 capture 0 line
capture1inputTimer 2 capture 1 line
capture2inputTimer 2 capture 2 line
capture3inputTimer 2 capture 3 line
t2inputTimer 2 clock line
t2exinputTimer 2 control
scliinputMaster/Slave I2C clock line input
sdaiinputMaster/Slave I2C data input
tdiinputDoCDTM TAP data input
tckinputDoCDTM TAP clock line
tmsinputDoCDTM TAP mode select
port0i (7:0)inputPort 0 input
port1i (7:0)inputPort 1 input
port2i (7:0)inputPort 2 input
port3i (7:0)inputPort 3 input
ramdatai (7:0)inputData bus from internal data memory
int0inputExternal interrupt 0
int1inputExternal interrupt 1
int2inputExternal interrupt 2
int3inputExternal interrupt 3
int4inputExternal interrupt 4
int5inputExternal interrupt 5
int6inputExternal interrupt 6
xdatai (7:0)inputData bus from external memories
readyinputExternal memory data ready
sfrdatai (7:0)inputData bus from user SFRs
rxd1iinputSerial receiver input 1
prgramdata (7:0)inputData bus from internal RAM program memory
prgromdata (7:0)inputData bus from internal ROM program memory
mosiinputSPI Master Output - Slave input
misoinputSPI Master input - Slave output
ssinputSPI slave select
sckinputSPI clock line
rxclkinputEthernet receive clock
rxdvinputEthernet receive data valid
rxerinputEthernet receive error
rxdata (3:0)inputEthernet receive data
qmr (7:0)inputRX DPRAM data output
txclkinputEthernet transmit clock
crsinputEthernet carrier sense
colinputEthernet collision detection
qmt (7:0)inputTX DPRAM data output
mdiinputManagement data input
sxdmdatai (7:0)inputData bus from sync external data memory (SXDM)
rxd0ooutputSerial receiver output 0
txd0outputSerial transmitter output 0
sclooutputMaster/Slave I2C clock output
sclhsoutputHigh speed Master I2C clock line
sdaooutputMaster/Slave I2C data output
tdooutputDoCDTM TAP data output
rtckoutputDoCDTM return clock
port0o (7:0)outputPort 0 output
port1o (7:0)outputPort 1 output
port2o (7:0)outputPort 2 output
port3o (7:0)outputPort 3 output
ramdatao (7:0)outputData bus for internal data memory
ramaddr (7:0)outputRAM address bus
ramoeoutputInternal data memory read
ramweoutputInternal data memory write enable
xdatao (7:0)outputData bus for external memories
xdatazoutputTurn xdata bus into "Z" state
xaddr (23:0)outputAddress bus for external memories
xprgrdoutputExternal program memory read
xprgwroutputExternal program memory write
xdatardoutputExternal data memory read
xdatawroutputExternal data memory write
sfrdatao (7:0)outputData bus for user SFRs
sfrweoutputUser SFRs write enable
sfroeoutputUser SFRs read
sfraddr (6:0)outputUser SFRs address bus
rxd1ooutputSerial receiver output 1
txd1outputSerial transmitter line 1
prgaddr (15:0)outputInternal program memory address bus
prgdatao (7:0)outputData bus for internal program memory
prgramwroutputInternal program memory write
stopoutputStop mode indicator
pmmoutputPower management mode indicator
sso (7:0)outputSlave Select outputs
dmr (7:0)outputRX DPRAM data input
waddrmr (10:0)outputRX DPRAM write address
raddrmr (10:0)outputRX DPRAM read address
enrmroutputRX DPRAM read enable
enwmroutputRX DPRAM write enable
txdata (3:0)outputEthernet transmit data
txenoutputEthernet transmit enable
txeroutputEthernet transmit error
dmt (7:0)outputTX DPRAM data input
waddrmt (10:0)outputTX DPRAM write address
raddrmt (10:0)outputTX DPRAM read address
enrmtoutputTX DPRAM read enable
enwmtoutputTX DPRAM write enable
mdooutputManagement data output
mdcoutputManagement clock
mdoeoutputManagement data output enable
sxdmaddr (15:0)outputSync XDATA memory address bus (SXDM)
sxdmdatao (7:0)outputData bus for Sync XDATA memory (SXDM)
sxdmoeoutputSync XDATA memory read (SXDM)
sxdmweoutputSync XDATA memory write (SXDM)

Block Diagram

Control UnitIt performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages execution of all microcontroller tasks.
iprgramsize (2:0)
iprgromsize (2:0)
Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.
TimersSystem timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
t0
t1
gate0
gate1
UART0Universal Asynchronous Receiver and Transmitter module is full duplex, which means, it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of a second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in the system).
rxd0i
rxd0o
txd0
Compare Capture UnitThe compare/capture/reload unit is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing, such as pulse generation, pulse width modulation, measurements etc.
capture0
capture1
capture2
capture3
Timer 2Timer 2 - Second system timer module contains one 16-bit configurable timer: Timer 2 (TH2, TL2), capture registers (RLDH, RLDL) and Timer 2 Mode (T2MOD) register. It can work as a 16-bit timer / counter, 16-bit auto-reload timer / counter. It also supports compare capture unit (if present in the system). It can be used as clock source for UART0.
t2
t2ex
Slave I2C UnitI2C bus controller is a Slave module. The core incorporates all features required by I2C specification. It works as a slave transmitter/receiver, depending on working mode, determined by a master device. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.
Master I2C UnitI2C bus controller is a Master module. The core incorporates all features required by I2C specification. It supports both 7-bit and 10-bit addressing modes on the I2C bus and works as a master transmitter and receiver. It can be programmed to operate with arbitration and clock synchronization, to allow it to operate in multi-master systems. Built-in timer enables operation within wide range of the input frequencies. The timer allows to achieve any non-standard clock frequency. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.
scli
sdai
sclo
sclhs
sdao
DoCDTM TTAG DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes TTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
tdi
tck
tms
tdo
rtck
ALUArithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.
I/O PortsBlock contains 8051's general purpose I/O ports. Each of the port's pin can be read/written as a single bit or as a 8-bit bus P0, P1, P2, P3.
port0i (7:0)
port1i (7:0)
port2i (7:0)
port3i (7:0)
port0o (7:0)
port1o (7:0)
port2o (7:0)
port3o (7:0)
Internal Data Memory InterfaceInterface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.
ramdatao (7:0)
ramaddr (7:0)
ramdatai (7:0)
ramoe
ramwe
Extended Interrupt ControllerInterrupt Controller module is responsible for the interrupt manage system, for the external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers.
int0
int1
int2
int3
int4
int5
int6
External Memory InterfaceContains memory access related registers, such as Data Page High (DPH), Data Page Low (DPL) and Data Page Pointer (DPP) registers. It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by the user. This feature is called Program Memory Wait States and it allows core, to work with different speed program memories.
xdatai (7:0)
xdatao (7:0)
xdataz
xaddr (23:0)
ready
xprgrd
xprgwr
xdatard
xdatawr
SFRs InterfaceSpecial Function Registers interface - controls access to externally connected peripherals, through SFR bus.
sfrdatai (7:0)
sfrdatao (7:0)
sfrwe
sfroe
sfraddr (6:0)
UART1Universal Asynchronous Receiver and Transmitter module is full duplex - it can transmit and receive concurrently. It includes Serial Configuration register (SCON1), serial receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, which means, it can commence reception of a second byte before the previously received byte has been read from the receive register. Writing to SBUF1, loads the transmit register and reading SBUF1, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by Timer 1.
rxd1i
rxd1o
txd1
Watchdog TimerThe watchdog timer is a 27-bit counter, which is incremented in every system clock period (CLK pin). It performs system protection against software upsets.
Program Memory InterfaceProgram Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.
prgramdata (7:0)
prgromdata (7:0)
prgaddr (15:0)
prgdatao (7:0)
prgramwr
Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It is highly desirable, when microcontroller is planned to be used in portable and power critical applications.
stop
pmm
Floating Point Math UnitFPMU contains floating arithmetic point xIEEE-754, compliant instructions (C float, int, long int types supported). It is used to execute single precision floating point operations such as: addition, subtraction, multiplication, division, square root, comparison absolute value of number and change of sign. Basing on specialized CORDIC algorithm, full set of trigonometric operations are also allowed: sine, cosine, tangent, arctangent. It also has built-in integer to floating point and vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and 32-bit signed integers. This unit has included standard software interface, which enables easy usage and interfacing with user's C/ASM written programs.
SPI UnitIt is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communication in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data transfer rate up to CLK/4. Clock control logic allows to select the clock polarity and to choose the two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made, to write data to the serial shift register, while the transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers, if more than one SPI device simultaneously attempts to become bus master.
mosi
miso
ss
sck
sso (7:0)
MDU - Multiply Divide UnitMultiply Divide Unit - It's a fixed point fast 16-bit and 32-bit multiplication and division unit. It provides shift and normalize operations. All operations are performed using unsigned integer numbers. The MDU contains MD0 to MD5 operands, the result registers and one control register, called ARCON. This unit has included standard software interface, which allows easy usage and interfacing with user C/ASM written programs.
DMAC - 10/100 Mb Media Access ControllerThe DMAC is a hardware implementation of media access control protocol, defined by the IEEE standard. DMAC, in cooperation with external PHY device, enables network functionality in design. It is capable of transmitting and receiving Ethernet frames, to and from the network. Half and full duplex modes are supported at 10 and 100 Mbit/s speed. The DMAC provides static configuration of PHY IC. Design is technology independent and thus can be implemented in various process technologies. This core strictly conforms to IEEE 802.3 standard.
rxclk
rxdv
rxer
rxdata (3:0)
qmr (7:0)
dmr (7:0)
waddrmr (10:0)
raddrmr (10:0)
enrmr
enwmr
txclk
crs
col
txdata (3:0)
txen
txer
qmt (7:0)
dmt (7:0)
waddrmt (10:0)
raddrmt (10:0)
enrmt
enwmt
mdo
mdc
mdoe
mdi
SXDM interfaceSynchronous eXternal Data Memory (SXDM) Interface – contains XDATA memory access related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables, frequently accessed by CPU, improving overall performance of application.
sxdmdatai (7:0)
sxdmaddr (15:0)
sxdmdatao (7:0)
sxdmoe
sxdmwe
MDU32 - 32-bit Multiply Divide UnitIt is a fixed point, fast 16-bit and 32-bit multiplication and division unit. It supports unsigned and 2's complement signed integer operands. The MDU32 is controlled by dedicated direct memory access module (called DMA). All arguments and result registers, are automatically read and written back by internal DMA. This unit has included standard software interface, which allows easy usage and interfacing with user C/ASM written programs. This module is a modern replacement for older MDU.
reset
clk
SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.
Internal data bus 8-bit internal data bus

Units

Control Unit
It performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages execution of all microcontroller tasks.
Opcode Decoder
Performs an opcode decoding instruction and control functions for all other blocks.
Timers
System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.

UART0
Universal Asynchronous Receiver and Transmitter module is full duplex, which means, it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of a second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in the system).
Compare Capture Unit
The compare/capture/reload unit is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing, such as pulse generation, pulse width modulation, measurements etc.
Timer 2
Timer 2 - Second system timer module contains one 16-bit configurable timer: Timer 2 (TH2, TL2), capture registers (RLDH, RLDL) and Timer 2 Mode (T2MOD) register. It can work as a 16-bit timer / counter, 16-bit auto-reload timer / counter. It also supports compare capture unit (if present in the system). It can be used as clock source for UART0.

Slave I2C Unit
I2C bus controller is a Slave module. The core incorporates all features required by I2C specification. It works as a slave transmitter/receiver, depending on working mode, determined by a master device. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.
Master I2C Unit
I2C bus controller is a Master module. The core incorporates all features required by I2C specification. It supports both 7-bit and 10-bit addressing modes on the I2C bus and works as a master transmitter and receiver. It can be programmed to operate with arbitration and clock synchronization, to allow it to operate in multi-master systems. Built-in timer enables operation within wide range of the input frequencies. The timer allows to achieve any non-standard clock frequency. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.
DoCDTM TTAG
DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes TTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.

ALU
Arithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.
I/O Ports
Block contains 8051's general purpose I/O ports. Each of the port's pin can be read/written as a single bit or as a 8-bit bus P0, P1, P2, P3.
Internal Data Memory Interface
Interface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.

Extended Interrupt Controller
Interrupt Controller module is responsible for the interrupt manage system, for the external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers.
External Memory Interface
Contains memory access related registers, such as Data Page High (DPH), Data Page Low (DPL) and Data Page Pointer (DPP) registers. It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by the user. This feature is called Program Memory Wait States and it allows core, to work with different speed program memories.
SFRs Interface
Special Function Registers interface - controls access to externally connected peripherals, through SFR bus.

UART1
Universal Asynchronous Receiver and Transmitter module is full duplex - it can transmit and receive concurrently. It includes Serial Configuration register (SCON1), serial receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, which means, it can commence reception of a second byte before the previously received byte has been read from the receive register. Writing to SBUF1, loads the transmit register and reading SBUF1, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by Timer 1.
Watchdog Timer
The watchdog timer is a 27-bit counter, which is incremented in every system clock period (CLK pin). It performs system protection against software upsets.
Program Memory Interface
Program Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.

Power Management Unit
Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It is highly desirable, when microcontroller is planned to be used in portable and power critical applications.
Floating Point Math Unit
FPMU contains floating arithmetic point xIEEE-754, compliant instructions (C float, int, long int types supported). It is used to execute single precision floating point operations such as: addition, subtraction, multiplication, division, square root, comparison absolute value of number and change of sign. Basing on specialized CORDIC algorithm, full set of trigonometric operations are also allowed: sine, cosine, tangent, arctangent. It also has built-in integer to floating point and vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and 32-bit signed integers. This unit has included standard software interface, which enables easy usage and interfacing with user's C/ASM written programs.
SPI Unit
It is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communication in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data transfer rate up to CLK/4. Clock control logic allows to select the clock polarity and to choose the two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made, to write data to the serial shift register, while the transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers, if more than one SPI device simultaneously attempts to become bus master.

MDU - Multiply Divide Unit
Multiply Divide Unit - It's a fixed point fast 16-bit and 32-bit multiplication and division unit. It provides shift and normalize operations. All operations are performed using unsigned integer numbers. The MDU contains MD0 to MD5 operands, the result registers and one control register, called ARCON. This unit has included standard software interface, which allows easy usage and interfacing with user C/ASM written programs.
DMAC - 10/100 Mb Media Access Controller
The DMAC is a hardware implementation of media access control protocol, defined by the IEEE standard. DMAC, in cooperation with external PHY device, enables network functionality in design. It is capable of transmitting and receiving Ethernet frames, to and from the network. Half and full duplex modes are supported at 10 and 100 Mbit/s speed. The DMAC provides static configuration of PHY IC. Design is technology independent and thus can be implemented in various process technologies. This core strictly conforms to IEEE 802.3 standard.
SXDM interface
Synchronous eXternal Data Memory (SXDM) Interface – contains XDATA memory access related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables, frequently accessed by CPU, improving overall performance of application.

MDU32 - 32-bit Multiply Divide Unit
It is a fixed point, fast 16-bit and 32-bit multiplication and division unit. It supports unsigned and 2's complement signed integer operands. The MDU32 is controlled by dedicated direct memory access module (called DMA). All arguments and result registers, are automatically read and written back by internal DMA. This unit has included standard software interface, which allows easy usage and interfacing with user C/ASM written programs. This module is a modern replacement for older MDU.