Digital Core Design

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DQSPI

Serial Peripheral Interface – Master/Slave with single, dual and quad SPI Bus support

    The DQSPI is a revolutionary quad SPI designed to offer the fastest available operations for any serial SPI memory. It is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Moreover, IP Core supports all 8, 16, 32 bit processors available on the market.

    The DQSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It lets the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it’s capable of interprocessor communications in a multi‐master system.
    A serial clock line (SCK) synchronizes shifting and sampling of the information on the four serial data lines. In the Single SPI mode data is simultaneously transmitted and received, in DUAL and QUAD SPI modes – data is shifted in or out on respectively two or four data lines at once. Transfer speed can additionally be doubled by using the DDR protocol (Double Data Rate, this feature allows the DQSPI to transfer/receive data on both falling and rising edges of SCK. DDR together with the QUAD SPI transfer allows the 8 bits of data to be sent/received within single SCK clock cycle. This makes the DQSPI perfect for systems where performance is essential where code can be moved from non-volatile memory to fast RAM, or for systems where device size and cost are key, where program code can be executed directly from non-volatile memory using an approach known as Execute-in-Place.
    DCD’s IP Core is a technology independent design that can be implemented in a variety of process technologies. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. Clock control logic allows a selection of clock polarity, phase and a choice of four fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. Error‐detection logic is included to support interprocessor communications.
    A write‐collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode‐fault detector automatically disables DQSPI output drivers, if more than one SPI device simultaneously attempts to become bus master. The DQSPI supports two DMA modes: single transfer and multi‐transfer. These modes allow DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multi-ple byte transfers.
    DQSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements.

    Watch the DQSPI presentation on DCD's You Tube:

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    Key Features

    • Operates with 8, 16 and 32 bit CPUs
    • Full duplex synchronous serial data transfer
    • DMA support
    • Support for 32, 16 and 8 bit systems
    • Support for various system Bus Standards
    • Single, Dual and Quad SPI transfer
    • DDR support (Double Data Rate)
    • Optionally available Execute-in-Place
    • Multimaster system supported
    • Optional FIFO size extension (128, 256, 512B)
    • Up to 8 SPI slaves can be addressed
      • Software Slave Select Output – SSO ‐ selection
      • Automatic Slave Select outputs assertion during each byte transfer
    • System error detection
    • Interrupt generation
    • Various Bit rates supported
    • Bit rate in fast SPI Mode ½ CLK
    • Four transfer formats
    • Simple SPU and DMA interface
    • Fully synthesizable, static synchronous de-sign with no internal tri‐states

    Applications

    • Embedded microprocessor boards
    • Consumer and professional audio/video
    • Home and automotive radio
    • Low-power applications
    • Communication systems
    • Digital multimeters

    Symbol

     mi
     si
    mo 
    so 
     scki
    scko 
     ss
    scken 
    sso (7:0) 
    int 
    soen 
     datai (7:0)
     rd
     wr
     addr (1:0)
     cs
    datao (7:0) 

    Pins description

    PinTypeDescription
    miinputMaster serial data input
    siinputSlave serial data input
    sckiinputSPI clock input
    ssinputSlave select
    datai (7:0)inputData bus input
    rdinputProcessor read strobe
    wrinputProcessor write strobe
    addr (1:0)inputProcessor address lines
    csinputChip select
    mooutputMaster serial data output
    sooutputSlave serial data output
    sckooutputSPI clock output
    sckenoutputSPI clock output enable
    sso (7:0)outputSlave select outputs
    intoutputInterrupt request
    soenoutputSlave output enable
    datao (7:0)outputData bus output

    Block Diagram

    TX FIFOThe Tx portion of the DSPI_FIFO transmits data through SO/MO, as soon as the CPU loads a byte into the Tx FIFO in Master mode. In Slave mode, the transmission is started after correct edge of the SCK signal. The DSPI_FIFO will prevent loads to the Tx FIFO, if it currently holds 64 (128, 256, 512) characters (depending on SFCR [5] bit value and selected FIFO size). Loading to the Tx FIFO again will be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx.
    Shift registerShift register is a core element of every SPI system. It is single buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter, until the previous transaction is complete. However, received data is transferred into a parallel read data buffer, so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer, before the next serial character is ready to be transferred, no overrun condition will occur. When an SPI transfer occurs, an 8-bit character is shifted out on data pin, while a different 8-bit character is simultaneously shifted in a second data pin. There is also another way to view this transfer, while 8-bit shift register in the master and another 8-bit shift register in the slave are connected, as a circular 16-bit shift register. When transfer occurs, this distributed shift register is moved 8-bit positions; thus, the characters in the master and slave are effectively exchanged.
    mi
    mo
    si
    so
    RX FIFOThe Rx FIFO can be 64 (128, 256, 512) levels deep, it receives data until the number of bytes in the FIFO, equals the selected interrupt trigger level. At that time, if interrupt is enabled, the DSPI_FIFO will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it is full, and will not accept any next byte. Any more data entering the Rx shift register will set the Over-run Error flag.
    SPI Clock LogicSoftware can select any from four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow master device communication with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral.
    scki
    scko
    SPI ControllerThe SPI Controller manages the Master/Slave operation and controls the transmission. It also manages the transmission speed and format (Phase and polarity). Controller itself generates interrupt request and detects transmission errors.
    scken
    ss
    sso (7:0)
    int
    soen
    Control RegistersThe Control Registers module contains all DSPI internal data, control and status registers.

    SPI Data Register (SPDR) is in fact double register - write only transmitter data register and read only receiver data register.

    Control Register may be read or written at any time, is used to configure the DSPI system. This register controls the mode of transmission (Master, Slave), polarity and phase of SPI Clock and transmission speed.

    Status Register (SPSR) contains flags, indicating the completion of transfer or occurrence of system errors. All flags are set automatically when the corresponding event occur and cleared by software sequence.

    Slave Select Control Register configures which slave select output should be driven while SPI master transfer. Contents of SSCR register is automatically assigned on SS7O-SS0O pins when DSPI master transmission starts.

    FIFO Control Register (FCR) available only in DSPI_FIFO mudule equipped with the FIFOs transmitter and receiver. FCR contains control bit, which configure receiver trigger level, enables FIFO mode, defines FIFO size and enables DMA mode.
    datai (7:0)
    datao (7:0)
    rd
    wr
    addr (1:0)
    cs
    SPI bus SPI virtual bus

    Units

    TX FIFO
    The Tx portion of the DSPI_FIFO transmits data through SO/MO, as soon as the CPU loads a byte into the Tx FIFO in Master mode. In Slave mode, the transmission is started after correct edge of the SCK signal. The DSPI_FIFO will prevent loads to the Tx FIFO, if it currently holds 64 (128, 256, 512) characters (depending on SFCR [5] bit value and selected FIFO size). Loading to the Tx FIFO again will be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx.
    Shift register
    Shift register is a core element of every SPI system. It is single buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter, until the previous transaction is complete. However, received data is transferred into a parallel read data buffer, so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer, before the next serial character is ready to be transferred, no overrun condition will occur. When an SPI transfer occurs, an 8-bit character is shifted out on data pin, while a different 8-bit character is simultaneously shifted in a second data pin. There is also another way to view this transfer, while 8-bit shift register in the master and another 8-bit shift register in the slave are connected, as a circular 16-bit shift register. When transfer occurs, this distributed shift register is moved 8-bit positions; thus, the characters in the master and slave are effectively exchanged.
    RX FIFO
    The Rx FIFO can be 64 (128, 256, 512) levels deep, it receives data until the number of bytes in the FIFO, equals the selected interrupt trigger level. At that time, if interrupt is enabled, the DSPI_FIFO will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it is full, and will not accept any next byte. Any more data entering the Rx shift register will set the Over-run Error flag.

    SPI Clock Logic
    Software can select any from four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow master device communication with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral.
    SPI Controller
    The SPI Controller manages the Master/Slave operation and controls the transmission. It also manages the transmission speed and format (Phase and polarity). Controller itself generates interrupt request and detects transmission errors.
    Control Registers
    The Control Registers module contains all DSPI internal data, control and status registers.

    SPI Data Register (SPDR) is in fact double register - write only transmitter data register and read only receiver data register.

    Control Register may be read or written at any time, is used to configure the DSPI system. This register controls the mode of transmission (Master, Slave), polarity and phase of SPI Clock and transmission speed.

    Status Register (SPSR) contains flags, indicating the completion of transfer or occurrence of system errors. All flags are set automatically when the corresponding event occur and cleared by software sequence.

    Slave Select Control Register configures which slave select output should be driven while SPI master transfer. Contents of SSCR register is automatically assigned on SS7O-SS0O pins when DSPI master transmission starts.

    FIFO Control Register (FCR) available only in DSPI_FIFO mudule equipped with the FIFOs transmitter and receiver. FCR contains control bit, which configure receiver trigger level, enables FIFO mode, defines FIFO size and enables DMA mode.