Digital Core Design

The Power of Intellectual Property

The DHDLC IP Core provides versatile support for widely used HDLC transmission protocol. It manages the bit stuffing process, and both address appending and detection. And if it’s not enough, let’s just mention that DCD’s IP Core supports CRC16 and CRC32 computation.
Increased system performance and reduced CPU overload is a must be, thanks to the presence of separate receiver and transmitter FIFO buffers, maskable interrupt and DMA interface request.
The DHDLC is a fully scalable IP Core which makes it a perfect solution, both for hi-end and deeply embedded projects. It’s tailored to your project needs - can be provided with:

+ small 8-bit SRAM-like interface;

+ 32-bit full AXI4 slave interface with burst support;

+ AXI4Lite interface;

+ AHB and APB slave interfaces.

The optional Frame Status Buffer stores the information about the frames sizes and error conditions. Moreover, the size of the receiver and transmitter FIFO buffers is configurable. You can also easily remove unused features before the synthesis process.
All of that and much more make the DHDLC an ideal solution for very popular higher level protocols implementations like e.g. PPP (Point-to-Point), X.25, V.42, LAB-B, SDLC, ISDN and many others. 


Key Features

  • Two separate receiver and transmitter interfaces.
  • Two separate, configurable FIFO buffers for receiver and transmitter
  • Bit stuffing and unstuffing
  • Address recognition for receiver and address insertion for transmitter
  • Two or one byte address field
  • CRC-16 and CRC-32 computation and checking
  • Collision detection
  • Byte alignment error detection
  • Programmable number of bits for idle detection
  • NRZI coding support
  • Shared flags, shared zeroes support
  • Pad fill with flags option
  • Transmitter clock generation
  • 8-bit, 16-bit, 32-bit CPU interface
  • Interrupt output for handling control flags and FIFOs’ filling
  • Configurable core parameters
     

Applications

  • CPU based applications with serial interface based on HDLC/SDLC protocol
  • Telecommunication

Design Features

The DHDLC IP core is full synchronous with one clock domain design. All parameters are configurable by CPU. But there is also capability for setting parameters by modification constants in source file. There is no need to wasting silicon resources for unused features and constant settings.


Symbol

 rst
 clk
 addr (3:0)
 datai (7:0)
 wr
 rd
 cs
datao (7:0) 
irq 
 rxd
 rxclk
 txclk
txd 
txclko 
 cxd
txclken 
 rxdatai (7:0)
 txdatai (7:0)
 txdmaclr
 rxdmaclr
rxdatao (7:0) 
rxwraddr (3:0) 
rxrdaddr (3:0) 
rxrd 
rxwr 
txdatao (7:0) 
txrdaddr (3:0) 
txwraddr (3:0) 
txrd 
txwr 
txdmareq 
rxdmareq 

Pins description

PinTypeDescription
rstinputGlobal reset
clkinputGlobal clock
addr (3:0)inputCPU address bus input
datai (7:0)inputCPU Data bus input
wrinputCPU write
rdinputCPU read signal
csinputDHDLC Chip Select input
rxdinputReceiver serial data input
rxclkinputReceiver clock input
txclkinputTransmitter clock input
cxdinputCollision detect input
rxdatai (7:0)inputRX FIFO data input
txdatai (7:0)inputTX FIFO data input
txdmaclrinputTX DMA request clear
rxdmaclrinputRX DMA request clear
datao (7:0)outputCPU Data bus output
irqoutputDHDLC Interrupt request to CPU
txdoutputTransmitter serial data output
txclkooutputTransmitter clock output
txclkenoutputTransmitter clock output enable
rxdatao (7:0)outputRX FIFO data output
rxwraddr (3:0)outputRX FIFO Write Address
rxrdaddr (3:0)outputRX FIFO read address
rxrdoutputRX FIFO read
rxwroutputRX FIFO write
txdatao (7:0)outputTX FIFO data output
txrdaddr (3:0)outputTX FIFO read address
txwraddr (3:0)outputTX FIFO write address
txrdoutputTX FIFO read
txwroutputTX FIFO write
txdmareqoutputTX DMA service request
rxdmareqoutputRX DMA service request

Block Diagram

CPU InterfacePerforms operations of reading and writing internal registers of the IP core. It also manages interrupt activity, sets and clears flags.
addr (3:0)
datai (7:0)
datao (7:0)
wr
rd
cs
irq
Serial InterfaceDirect HDLC/SDLC interface. Realizes tasks of bit stuffing and unstuffing, NRZI coding, collision detection, CRC calculation, flags and abort detection, idle detection and synchronizes serial inputs with main clock domain
rxd
rxclk
txd
txclk
txclko
Control UnitMain control unit. This module is responsible for managing other blocks. Mainly it controls and services requests from CPU interface module and forms data for HDLC frame. It also realizes some features of HDLC control like address recognition and insertion, padding, etc.
cxd
Clock DividerGenerates divided clock signal for TXCLKO output.
txclken
FIFO ControlManages access to FIFO buffers of receiver and transmitter. It also generates current state of FIFO flags. The flags indicates, among others, that FIFO are empty or full. It also indicates events of FIFO's under or overflowing.
rxdatai (7:0)
rxdatao (7:0)
rxwraddr (3:0)
rxrdaddr (3:0)
rxrd
rxwr
txdatai (7:0)
txdatao (7:0)
txrdaddr (3:0)
txwraddr (3:0)
txrd
txwr
txdmareq
txdmaclr
rxdmareq
rxdmaclr
rst
clk
Control Bus

Units

CPU Interface
Performs operations of reading and writing internal registers of the IP core. It also manages interrupt activity, sets and clears flags.
Serial Interface
Direct HDLC/SDLC interface. Realizes tasks of bit stuffing and unstuffing, NRZI coding, collision detection, CRC calculation, flags and abort detection, idle detection and synchronizes serial inputs with main clock domain
Control Unit
Main control unit. This module is responsible for managing other blocks. Mainly it controls and services requests from CPU interface module and forms data for HDLC frame. It also realizes some features of HDLC control like address recognition and insertion, padding, etc.

Clock Divider
Generates divided clock signal for TXCLKO output.
FIFO Control
Manages access to FIFO buffers of receiver and transmitter. It also generates current state of FIFO flags. The flags indicates, among others, that FIFO are empty or full. It also indicates events of FIFO's under or overflowing.